Showing 37–48 of 128 results

IC 74HC132 RCA IC 74HC132 Quad 2-Input NAND Schimtt Trigger

15.99

IC 74HC132 Quad 2-Input NAND Schimtt Trigger

 

IC 74HC139 74LS139 Dual 2-to-4 line Decoder/Demultiplexer IC (74139 IC) DIP-16 Package

11.65
The 74LS139 comprises two separate two-line-to-four line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design. These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. Features:- • Designed specifically for high speed: Memory decoders Data transmission systems • 74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers • Schottky clamped for high performance • Typical propagation delay (3 levels of logic) is 21 ns • Typical power dissipation  is 34 mW Specifications:-
Parameter Specification
Supply Voltage (VCC) 7 V
Input Voltage (VI) 7 V
Operating free-air temperature range 0°C to +70°C
Storage temperature range –65°C to +150°C
Related Document:-  74LS139 IC Datasheet

IC 74HC164 ST 74HC164 8-Bit Serial In/Parallel out Shift Register IC (74164 IC) DIP-14 Package

19.50
74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices. This 8-bit shift register has gated serial inputs and CLEAR. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features:-
  • Typical operating frequency: 50 MHz
  • Typical propagation delay: 19 ns (clock to Q)
  • Wide operating supply voltage range: 2V to 6V
  • Low input current: 1 µA maximum
  • Low quiescent supply current: 80 µA maximum (74HC Series)
  • Fanout of 10 LS-TTL loads
Specifications:-
Parameter Min Max Unit
Supply Voltage (VCC) 2 6 V
DC Input or Output Voltage (VIN, VOUT) 0 Vcc V
Operating Temperature Range (TA) −4 -40 85 °C
Input Rise or Fall Times
VCC = 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 6.0V 400 ns
Related Document:-  74HC164 IC Datasheet

IC 74HC245 74LS245 3-State Octal Bus Transceiver IC (74245 IC) DIP-20 Package

18.99
The 74LS245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The device allows data transmission from the A Bus to the B Bus or from the B Bus to the A Bus depending upon the logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated. Features:-  • Bi-Directional bus transceiver in a high-density 20-pin package • 3-STATE outputs drive bus lines directly • PNP inputs reduce DC loading on bus lines • Hysteresis at bus inputs improve noise margins • Typical propagation delay times, port-to-port 8 ns • Typical enable/disable times 17 ns • IOL (sink current) 24 mA • IOH (source current) −15 mA Specifications:-
Parameter Specification
Supply Voltage (VCC) 7 V
Input Voltage (VI) 7 V
Operating free-air temperature range 0°C to +70°C
Storage temperature range –65°C to +150°C
Related Document:-  74LS245 IC Datasheet

IC 74LS00 74LS00 Quad 2 Input NAND Gate IC (7400 IC) DIP-14 Package

8.78
The 74LS00 is a 14 Pin Quad 2-Input NAND Gate IC. This device contains four independent gates each of which performs the logic NAND function. NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds  with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74LS logic family is functionally as well as pin-out compatible with the standard 74HC logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features:-
  • Four Independent NAND Gates
  • 14 Pin IC
  • Operating Temperature to 70 C
  • High-Speed Low Power CMOS Type
Related Document:-

IC 74LS02 74LS02 Quad 2-Input NOR Gate IC (7402 IC) DIP-14 Package

21.89
The 74LS02 is a 14 Pin Quad 2-Input NOR Gate IC. NOR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to HC gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features:-
  • Four Independent NOR Gates
  • 14 Pin IC
  • Operating Temperature to 70 Deg C
  • High-Speed CMOS Type
Related Document:-
* Product Images are shown for illustrative purposes only and may differ from actual product.

IC 74LS04 74LS04 Hex Inverter IC (7404 IC) DIP-14 Package

11.99
74LS04 is Hex Inverter NOT gate IC. It consists of six inverters which perform logical invert action. output of an inverter is complement of its input logic state i.e. when input is high its output is low and vice versa. device contains six independent gates each of which performs logic INVERT function. Operating voltage is 5V, high-level input voltage is 2V, and low-level input is 0.8V. Contains absolute maximum ratings over operating free-air temperature range, recommended operating conditions, electrical characteristics over recommended operating free-air temperature range. Features:-  
  • 6 Hex Inverters in a 14-Pin DIP Package
  • Outputs Directly Interface to CMOS, NMOS and TTL
  • Large Operating Voltage Range
  • Wide Operating Conditions
    Specifications:-  
  • Type: DIP Bipolar
  • Voltage Rating: 4.75 to 5.25V
  • Current Rating: Max. 16mA Output
  • Temperature Rating: 0 to 70Deg C
  • Number of: 14 Pins
  • Mounting: Through Hole
  Datasheet:- 74LS04 IC Datasheet 

IC 74LS08

14.00
Arduino Uno Rev3 Code: A000066 / Barcode: 7630049200050 Nunc per mollis pot enti amet imperdiet blandit dis eu sociosqu accumsan

IC CD40106

14.00
Arduino Uno Rev3 Code: A000066 / Barcode: 7630049200050 Nunc per mollis pot enti amet imperdiet blandit dis eu sociosqu accumsan

IC CD4013 HLF

12.00
Arduino Uno Rev3 Code: A000066 / Barcode: 7630049200050 Nunc per mollis pot enti amet imperdiet blandit dis eu sociosqu accumsan

IC IR2110 IR

90.00
Features:-
  • Floating channel designed for bootstrap operation Fully operational to +500V or +600V Tolerant to negative transient voltage dV/dt immune
  • Gate drive supply range from 10 to 20V
  • Undervoltage lockout for both channels
  • 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset
  • CMOS Schmitt-triggered inputs with pull-down
  • Cycle by cycle edge-triggered shutdown logic
  • Matched propagation delay for both channels
  • Outputs in phase with inputs